Integration of digital, analog, radio frequency, photonic and other devices into a complex System on Chip (“SoC”) is generally well known and has been previously demonstrated. (See, e.g., Reference 1). More recently, sensors, actuators, and biochips are also being integrated into these already powerful SoCs. SoC integration has been facilitated by advances in mixed system integration and the increase in the wafer sizes (e.g., currently about 300 mm and projected to be 450 mm by year 2018), which has resulted in a reduction in the cost per chip of such SOCs. (See, e.g., Reference 1). However, support for multiple capabilities, and mixed technologies, has increased the cost of ownership of advanced foundries. For instance, the cost of owning a foundry will be approximately $5 billion in year 2015. (See e.g., 15 Reference 2). Consequently, only large commercial foundries now manufacture such high performance, mixed system SoCs, especially at the advanced technology nodes. (See, e.g., Reference 3). Absent the economies of scale, many of the design companies cannot afford owning and acquiring expensive foundries, and therefore, outsource their design fabrication to “one-stop shop” foundries.
Globalization of Integrated Circuits (“IC”) design flow has led to several security vulnerabilities. If a design can be fabricated in a foundry that may not be under the direct control of the fabless design house, attacks such as reverse engineering, malicious circuit modification and Intellectual Property (“IP”) piracy can be possible. (See, e.g., Reference 3). An attacker, anywhere in the design flow, can reverse engineer the functionality of an IC/IP, and then steal and claim ownership of the IP. An untrusted IC foundry can overbuild ICs and sell them illegally. Additionally, rogue elements in the foundry can insert malicious circuits (e.g., hardware trojans) into the design without the designer's knowledge. (See, e.g., References 4 and 5). Due to these attacks, the semiconductor industry loses approximately $4 billion annually. (See, e.g., Reference 6).
Certain fabless semiconductor companies, such as Advanced Micro Devices, Inc. (“AMD”) and research agencies, such as Intelligence Advanced Research Projects Agency (“IARPA”) have proposed split manufacturing to thwart such attacks. (See, e.g., References 3; 8). In split manufacturing, the layout of the design can be split into the Front End Of Line (“FEOL”) layers and Back End Of Line (“BEOL”) layers which can then be fabricated separately in different foundries. The FEOL layers can consist of transistors and other lower metal layers (e.g., ≤M4) and the BEOL layers can consist of the top metal layers (e.g., >M4). Post fabrication, the FEOL, and BEOL wafers can be aligned and integrated together using either electrical, mechanical, or optical alignment techniques. The final ICs can be tested upon integration of the FEOL and BEOL wafers. (See, e.g., References 3; 8). The asymmetrical nature of the metal layers can facilitate split manufacturing. FIG. 1A shows an exemplary cross-section of IC, and FIG. 1B shows exemplary pitches of different metal layers for the 45 nm technology. (See, e.g., Reference 7). The top BEOL metal layers can be thicker and have a larger pitch than the bottom FEOL metal layers. Therefore, a designer can easily integrate the BEOL and FEOL wafers.
FIG. 2 shows an exemplary split manufacturing-aware IC design flow. A gate level netlist 205 can be partitioned 210 into blocks, which can then be floorplanned and placed. The transistors and wires inside a block can form the FEOL layers 215. The top metal wires connecting the blocks and the IO ports can form the BEOL layers 220. The BEOL 220 and FEOL 215 wires can be assigned to different metal layers and routed such that the wiring delay and routing congestion can be minimized. The layout 225 of the entire design can be split into two—one layout and can contain the FEOL layers 215, and the other layout can contain the BEOL layers 220. The two layouts can then be fabricated in two different foundries.
The fabricated FEOL 215 and BEOL layouts 220 can be obtained by a system integrator, and can then be integrated by using electrical, mechanical, or optical alignment techniques, and tested for defects. (See, e.g., Reference 8). The FEOL layout 215 can be first fabricated and then sent to a trusted second foundry where the BEOL layout 220 can be built on top of it. (See, e.g., Reference 8).
Split manufacturing can improve the security of the IC, as the FEOL and BEOL layers can be fabricated separately and combined post fabrication. This can prevent a single foundry (e.g., especially the FEOL foundry) from gaining full control of the IC. For instance, without the BEOL layers, an attacker in the FEOL foundry can neither identify the “safe” places within a circuit to insert trojans, nor pirate the designs without the BEOL layers. The economic benefit of split manufacturing can come from performing the low cost BEOL layer fabrication in-house and outsourcing the expensive FEOL layer fabrication. (See, e.g., Reference 3).
Transporting the FEOL wafers to the BEOL foundry, or transporting the FEOL and BEOL wafers to the SoC integrator, can present a challenge (e.g., these wafers can be thin and might crack or delaminate during transportation). An alignment of the FEOL and BEOL layers, and increase in die area to accommodate alignment structures, present a further challenge. Split manufacturing can also affect the signal integrity timing of the signals that span the FEOL and BEOL layers, and other design-for-manufacturability aspects. While several research projects from research agencies such as IARPA (see e.g., Reference 3) and companies such as AMD (see e.g., Reference 8) focus on addressing these challenges, and make it feasible to reap the benefits of split manufacturing, split manufacturing can be inherently insecure.
Thus, it may be beneficial to provide exemplary systems, methods and computer-accessible mediums to provided and/or secure split manufacturing, and which can address and/or overcome at least some of the deficiencies described herein above.